// // 09-Delta.spx // SYNC Generation, WrFrontEnd/RdFrontEnd // Delay of DTI nominal is 19. active_fe = ffff trigd = 7 FE_0 = 0 FE_1 = 1 FE_2 = 2 FE_3 = 3 FE_4 = 4 FE_5 = 5 FE_6 = 6 FE_7 = 7 FE_8 = 8 FE_9 = 9 FE_10 = A FE_11 = B FE_12 = C FE_13 = D FE_14 = E FE_15 = F TRAIL 10 // Start TEST#1 // Test inputs: RSIb // insert RSIb = 0 30 WR_REGISTER FEEN $active_fe // insert RSIb 30 RD_REGISTER FEEN 0xffff 30 WR_REGISTER FEEN $active_fe // End test#1 // Start test#2 // Test input: DCI // Test output: DTO, DTO2, SYNC 40 GLOBAL_RESET_FE 0x0 // End test#2 // Start test#3 // Test input: DCI, DTI<15:0>, DTIa<15:8>, AMSDSM // Test output: DTO, DTO2, CCK, CCKa, LD, LDa, DAO // insert AMSDSM = 1 and generate DTIa<15:8>|DTI<7:0>, DTI<15:8> = 0x00 30 WR_REGISTER CNT 0x0082 // 16-CCK, LD, 16-CCK 30 RD_FRONTEND 0 0xaaaaaaaa // insert AMSDSM = 0 and generate DTI<15:0>, DTIa<15:8> = 0x00 50 WR_REGISTER CNT 0x0082 // 16-CCK, LD, 16-CCK 30 RD_FRONTEND 0 0xaaaaaaaa // End test#3 // Start test#4 // Test input: DCI // Test output: STRO, LV1 50 WR_REGISTER CNT 8 30 WR_REGISTER CAL 401 30 ENABLE_DATATAKE 30 CAL // 38 - Range 0, Delay 1x1 50 TRIGGER // End test#4