#====================================================================== # DESIGN NAME: MCC_DSM # CUSTOMER: Roberto Beccherle of INFN - Genova # LIBRARY TYPE: cmos6sf25CoreLib dw_foundation.sldb Memory # REVISION: 1.00 # DATE: 01/Aug/2002 #====================================================================== # # Bottom side of the chip, from left to right # DTIAn_8_ 1 I # Primary Input DTIAp_8_ 2 I # Primary Input DTIAn_9_ 3 I # Primary Input DTIAp_9_ 4 I # Primary Input DTIAn_10_ 5 I # Primary Input DTIAp_10_ 6 I # Primary Input DTIAn_11_ 7 I # Primary Input DTIAp_11_ 8 I # Primary Input DTIAn_12_ 9 I # Primary Input DTIAp_12_ 10 I # Primary Input DTIAn_13_ 11 I # Primary Input DTIAp_13_ 12 I # Primary Input # # GND7 # Power Supply (ground) # VDD7 # Power Supply (vdd) # DTIAn_14_ 13 I # Primary Input DTIAp_14_ 14 I # Primary Input DTIAn_15_ 15 I # Primary Input DTIAp_15_ 16 I # Primary Input LDA 17 O # Primary Output CCKA 18 O # Primary Output TSTIN 19 I # Scan_in Port # # Right side of the chip, from bottom to top # # # GND0 # Power Supply (ground) # VDD0 # Power Supply (vdd) # LD 20 O # Primary Output CCK 21 O # Primary Output RSIb 22 I # Primary Input DTO2n 23 O # Primary Output DTO2p 24 O # Primary Output DTOn 25 O # Primary Output DTOp 26 O # Primary Output # # GND1 # Power Supply (ground) # VDD1 # Power Supply (vdd) # TSTOUT 27 O # Scan_out Port DCIn 28 I # Primary Input DCIp 29 I # Primary Input CKn 30 I # System Clock CKp 31 I # System Clock # # GND2 # Power Supply (ground) # VDD2 # Power Supply (vdd) # # # Top side of the chip, from right to left # TSTEN 32 I # Scan_mode_control Port RSOb 33 O # Primary Output DAO 34 O # Primary Output DTIn_0_ 35 I # Primary Input DTIp_0_ 36 I # Primary Input DTIn_15_ 37 I # Primary Input DTIp_15_ 38 I # Primary Input DTIn_1_ 39 I # Primary Input DTIp_1_ 40 I # Primary Input DTIn_14_ 41 I # Primary Input DTIp_14_ 42 I # Primary Input # # GND3 # Power Supply (ground) # VDD3 # Power Supply (vdd) # DTIn_2_ 43 I # Primary Input DTIp_2_ 44 I # Primary Input DTIn_13_ 45 I # Primary Input DTIp_13_ 46 I # Primary Input DTIn_3_ 47 I # Primary Input DTIp_3_ 48 I # Primary Input DTIn_12_ 49 I # Primary Input DTIp_12_ 50 I # Primary Input DTIn_4_ 51 I # Primary Input DTIp_4_ 52 I # Primary Input DTIn_11_ 53 I # Primary Input DTIp_11_ 54 I # Primary Input DTIn_5_ 55 I # Primary Input DTIp_5_ 56 I # Primary Input DTIn_10_ 57 I # Primary Input DTIp_10_ 58 I # Primary Input DTIn_6_ 59 I # Primary Input DTIp_6_ 60 I # Primary Input DTIn_9_ 61 I # Primary Input DTIp_9_ 62 I # Primary Input DTIn_7_ 63 I # Primary Input DTIp_7_ 64 I # Primary Input DTIn_8_ 65 I # Primary Input DTIp_8_ 66 I # Primary Input # # Left side of the chip, from top to bottom # # # GND4 # Power Supply (ground) # VDD4 # Power Supply (vdd) # LV1n 67 O # Primary Output LV1p 68 O # Primary Output STROn 69 O # Primary Output STROp 70 O # Primary Output # # GND5 # Power Supply (ground) # VDD5 # Power Supply (vdd) # XCKn 71 O # Primary Output XCKp 72 O # Primary Output XCKINn 73 I # System Clock XCKINp 74 I # System Clock SYNCn 75 O # Primary Output SYNCp 76 O # Primary Output AMSDSM 77 I # Primary Input # # GND6 # Power Supply (ground) # VDD6 # Power Supply (vdd) # # BIAS # Bias Pad (not to be tested) #