Specifications
- MCC-D2 Specifications: [PDF]
- Index: [PDF]
- 1.Introduction: [PDF]
- 2.Command Decoder (V.1.0): [PDF, readme]
- 3.Register Bank (V.1.0): [PDF]
- 4.Receiver Channel: [PDF]
- 5.Event Builder: [PDF]
- 6.Module Port: [PDF]
- 7.FE Port: [PDF]
- 8.Output Data Format (DRAFT): [PDF]
- 9.Input Data Format: [PDF]
- 10.Floorplan: [PDF]
Packaging Infos
- Pin list
- LDCC-84 Packaging:
Block Infos
Chip Test

- Working frequency and power consumption:
- IDD versus CK frequency and Maximum working frequency at nominal VDD (3.3 V) [HTML]
- IDD versus CK for VDD = 3.0, 3.5 and 4.0 V [HTML]
- Max CK frequency behavior with respect to VDD [HTML]
- Yield test (preliminary) [HTML]
- Delay circuit measurements:
- Delay linearity and range [HTML]
- Delay versus VDD [HTML]
- Test of LV1 command [HTML]
- Test of CAL command [HTML]
- Bug list [HTML]
Notes
After Hours meetings on MCC-D2 architecture specifications:
- December 1999: [PDF]
- September 1999: [PDF]

Please address comments or suggestions to: Giovanni Darbo
Last updated: Sun, Mar 11, 2001