Minute of the MCC-DSM Design Meeting held on 29th of January 2003
(Periodic meeting on MCC project progress)
Present: Roberto Beccherle, Giovanni Darbo, Guido Gagliardi, Paolo Morettini, Carlo Schiavi.
Status of MCC-I2 specs and implementation: Roberto makes a summary of what is already updated in the verilog code released in the CVS depository and what is still to be done (for rev.1 and 2). The main points are:
- RdFIFO output alignment: The delay between the issuing of RdFIFO command and the output data fluctuate by one clock cycle. This is due to the implementation of the OutputPort. Roberto claims that the fixing of the thing is not straightforward. Because the actual implementation has no consequences in the normal operation of the chip we decide to leave it like it is.
- Output pattern all 1: There was a request, by K.K. Gan, to implement an OutputPattern mode where there is always 1' s at the DTO/DTO2 outputs. This is for faster annealing of the VCSELs. We decided to implement this mode by setting the OM/OPAT bits in the CSR register to OM<1:0>=1x and OPAT=1.
ECR not in run mode: If a slow command is issued when the MCC is in run mode the chip goes to configuration mode and it is possible to look at PendingLv1FIFO's and to PendingLv1Fifo. If the MCC is rearmed (run mode) it is necessary to do a reset to the EventBuilder data path. This operation is usually accomplished by ECR fast command. The MCC-I1 implementation does not allow to issue an ECR in configuration mode and to execute it after setting run mode may generate spurious output. Possible solutions are a new slow command (SlowECR=10110.1011.1100) or to make active ECR in configuration mode. Roberto will study the better solution,
GlobalResetMCC to reset CMD block: The GlobalResetMCC command resets everything but the CMD block itself. The state machines of the CMD block go to the idle state, after power-up, after a well define time (<~130.000 clock cycles). The MCC-I1 is alive and responds to commands only if the CMD state machines are in the idle state. This latency is not a problem for system operation and the RSIb pin avoids this latency for chip test. The problem comes in case of Flex Hybrid test where the pin reset (RSIb) is no more accessible, and we would prefer to avoid the long initialisation time that correspond to useless test vectors. Roberto will try to see if exist a solution that does not imply a redesign of the CMD.
Errors at high LV1 rates (see minutes of 22/01/2003): Carlo has generated a sequence similar to the one that, according to Kevin, produces L1ID differences between FE's and he simulated it with the MCC-I1 verilog. No MCC-FLAG due to L1ID which comes from the MCC. Is it a real MCC-I1 bug or it comes from other components in the module or off detector responding in unexpected way?
EoE overflow (see minutes of 22/01/2003): Paolo and Roberto tried to reproduce the problem on a module, readout by a TPLL. Several error panels reported errors. There is apparently some inconsistency in the panels; some input from LBL is needed. Action: ask Kevin/John.
Output mode and playback: The MCC-I1 has the higher output data rates (40x2, 80x1 and 80x2) enabled by the OR of playback and run mode. This will be change by run mode only
Validation of the Verilog by SimPix: Additional test vectors have been written to detect the bugs in the MCC-I1 that have not been seen at the time of last chip submission. The script files, their descriptions and the result of the test are accessible on the page:
All the new added scripts find the bugs in the MCC-I1 and they execute correctly on the MCC-I1 (rev.1).
SimPix update: Paolo has fixed some of the association errors in the SimPix. Still a few others need to be fixed. Overlapped events can be generated by SimPIx script; Paolo explained how. Paolo found a bug in the C++ implementation of the MCC-I1: the BCID is always incremented by two instead than one. Carlo will fix it.
Schedule: We have checked the schedule (see minute 22/1/03) where the first milestone is foreseen for the 31st January. We believe that for the moment we are almost on track.
Chip size: Version 5 of Flex Hybrid leave about 0.5 mm additional space to grow for the MCC-I2 on its bottom side. The limit is the C1/C22 that are 0.95 mm below the MCC-I1 bottom side. There is still some room to grow on the 3 sides where there are the wirebonds (200 µm? now the wirebonds are 1.2 mm long centre to centre). Walter Ockenfels will provide an estimation of the minimum wire lengths. See figure of the Flex Hybrid v.5 with MCC-I1 overlaid.
- Irradiation analysis and new irradiation.
Guido is working on the analysis of the dynamic effect of SEU. We discussed of other control plots on the already analysed data.