/* analog_part.v - very simple model for the analog part of MARS_0-18 * * Author: Paolo Musico (I.N.F.N. Genova) * Date: 22 April 2004 * Rev: 1.0 * */ `define N_CH 18 module analog_part(ANODE, ANALOG_OUT, COMPARATOR_OUT, INTEGRATOR_FLAG, COARSE_DAC, FINE_DAC0, FINE_DAC1, FINE_DAC2, FINE_DAC3, FINE_DAC4, FINE_DAC5, FINE_DAC6, FINE_DAC7, FINE_DAC8, FINE_DAC9, FINE_DAC10, FINE_DAC11, FINE_DAC12, FINE_DAC13, FINE_DAC14, FINE_DAC15, FINE_DAC16, FINE_DAC17, ANALOG_SELECT, RD_ANALOG, RD_DYNODE, VMON0, VMON1, IMON0, IMON1, DYNODE, TRGH, TRGL, RSTb, GTU_CLOCK, CLOCK, RUN ); inout [`N_CH-1:0] ANODE; // Analog anode inputs inout ANALOG_OUT; // Analog output: anode or dynode memories output [`N_CH-1:0] COMPARATOR_OUT; // Comparator outputs output [`N_CH-1:0] INTEGRATOR_FLAG; // Integrator flag: write on analog memory input [7:0] COARSE_DAC; // Main dac value input [3:0] FINE_DAC0, FINE_DAC1, FINE_DAC2, // Channel dac values FINE_DAC3, FINE_DAC4, FINE_DAC5, FINE_DAC6, FINE_DAC7, FINE_DAC8, FINE_DAC9, FINE_DAC10, FINE_DAC11, FINE_DAC12, FINE_DAC13, FINE_DAC14, FINE_DAC15, FINE_DAC16, FINE_DAC17; input [7:0] ANALOG_SELECT; // Select which analog memory put on ANALOG_OUT input [`N_CH-1:0] RD_ANALOG; // Read pulses to take out the next value input RD_DYNODE; // Read pulses to take out the next value inout VMON0, VMON1, IMON0, IMON1; // Analog monitor V & I inout DYNODE; // Analog dynode input inout TRGH, TRGL; // Comparator outputs from dynode channel input RSTb, GTU_CLOCK, CLOCK, RUN; // Common control signals assign VMON0 = 0, VMON1 = 0, IMON0 = 0, IMON1 = 0; assign TRGH = 0, TRGL = 0; assign ANALOG_OUT = 0; assign COMPARATOR_OUT = ANODE; assign INTEGRATOR_FLAG = ANODE; endmodule