/* digital_part.v - Digital part for MARS_0-18 * * Author: Paolo Musico (I.N.F.N. Genova) * Date: 21 April 2004 * Rev: 1.0 */ `define N_CH 18 module digital_part(CHIP_X, CHIP_Y, CHIP_OR_OUT, CHIP_OR_IN, DISCR_OUT, ANODE, INTEGRATOR_FLAG, TEST_PULSE, COARSE_DAC, FINE_DAC0, FINE_DAC1, FINE_DAC2, FINE_DAC3, FINE_DAC4, FINE_DAC5, FINE_DAC6, FINE_DAC7, FINE_DAC8, FINE_DAC9, FINE_DAC10, FINE_DAC11, FINE_DAC12, FINE_DAC13, FINE_DAC14, FINE_DAC15, FINE_DAC16, FINE_DAC17, ANA_OUT_SELECT, RD_ANA_CH, RD_DYNODE_CH, GTU_CLOCK, RUN, ADC_SDATA, ADC_SCLK, ADC_CSb, ADDRESSED, DATA_OUT, DATA_IN, D_C, GA, CLOCK, RSTb); output [2:0] CHIP_X; // To X output pads (BUDD4P) output [5:0] CHIP_Y; // To Y output pads (BUDD4P) output CHIP_OR_OUT; // To Fast OR output pad (BU4P) input CHIP_OR_IN; // From Fast OR input pad (ISDP) output DISCR_OUT; // To Discriminator output pad (BU4P) input [`N_CH-1:0] ANODE; // From front end discriminators, to channels input [`N_CH-1:0] INTEGRATOR_FLAG; // From channel AFEE, to channels input TEST_PULSE; // From TEST input pad (ISDP), to channels output [7:0] COARSE_DAC; // To main DAC for coarse comparator threshold setting output [3:0] FINE_DAC0; // To Channel 0 local DAC for fine comparator threshold setting output [3:0] FINE_DAC1; // To Channel 1 local DAC for fine comparator threshold setting output [3:0] FINE_DAC2; // To Channel 2 local DAC for fine comparator threshold setting output [3:0] FINE_DAC3; // To Channel 3 local DAC for fine comparator threshold setting output [3:0] FINE_DAC4; // To Channel 4 local DAC for fine comparator threshold setting output [3:0] FINE_DAC5; // To Channel 5 local DAC for fine comparator threshold setting output [3:0] FINE_DAC6; // To Channel 6 local DAC for fine comparator threshold setting output [3:0] FINE_DAC7; // To Channel 7 local DAC for fine comparator threshold setting output [3:0] FINE_DAC8; // To Channel 8 local DAC for fine comparator threshold setting output [3:0] FINE_DAC9; // To Channel 9 local DAC for fine comparator threshold setting output [3:0] FINE_DAC10; // To Channel 10 local DAC for fine comparator threshold setting output [3:0] FINE_DAC11; // To Channel 11 local DAC for fine comparator threshold setting output [3:0] FINE_DAC12; // To Channel 12 local DAC for fine comparator threshold setting output [3:0] FINE_DAC13; // To Channel 13 local DAC for fine comparator threshold setting output [3:0] FINE_DAC14; // To Channel 14 local DAC for fine comparator threshold setting output [3:0] FINE_DAC15; // To Channel 15 local DAC for fine comparator threshold setting output [3:0] FINE_DAC16; // To Channel 16 local DAC for fine comparator threshold setting output [3:0] FINE_DAC17; // To Channel 17 local DAC for fine comparator threshold setting output [7:0] ANA_OUT_SELECT; // To analog mux: select which channel take out of the chip output [`N_CH-1:0] RD_ANA_CH; // Read pulse to take out next channel analog data output [3:0] RD_DYNODE_CH; // Read pulse to take out next dynode analog data input GTU_CLOCK; // Acquisition Gate, from input pad (ICCKxP or ISDP?) input RUN; // Aquire (1) or readout/test (0), from input pad (ISDP) input ADC_SDATA; // ADC serial data in, form input pad w/pullup (ISUP) output ADC_SCLK; // ADC conversion clock, to output pad (BU4P) output ADC_CSb; // ADC chip select - start conversion, to output pad (BU4P) output ADDRESSED; // chip was addressed, to output pad (BU4P) output DATA_OUT; // Serial data out, to output pad (BU4P) input DATA_IN; // Serial data in, from input pad (ISDP) input D_C; // Serial data/control select line, from input pad (ISDP) input [3:0] GA; // Geographical address, from input pad (ISDP) input CLOCK; // Main clock, from input pad (ICCKxP or ISDP?) input RSTb; // General reset active low, from input pad (ISUP) wire [`N_CH-1:0] channel_or, channel_xy; wire [8:0] data_fast; wire [15:0] data_slow, data_ana, wr_test_data; wire [`N_CH-1:0] rd_fast, rd_slow, wr_fast, wr_slow, en_fast, en_slow; wire [1:0] rd_ana, wr_ana, en_ana; wire [6:0] addr_fast_read, addr_fast_write, addr_slow_read, addr_slow_write; wire [10:0] addr_ana_rd, addr_ana_wr; wire [`N_CH-1:0] pix_enable, or_enable, xy_enable; wire [7:0] digital_threshold, gtu_sum_period; wire [7:0] discr_out_select, ana_reg_select, ana_auto_select; wire [31:0] load_sr, load_reg; wire run_enable, test_fast, test_slow, gtu_sum, sync, reset; wire auto_conv_enable; wire [`N_CH-1:0] ana_auto_rd_ch, ana_rd_command; wire [3:0] ana_auto_rd_dynode, dynode_rd_command; wire [2:0] id_fast_1st, id_slow_1st; wire [4:0] id_fast_main, id_slow_main; assign reset = ~RSTb; assign ANA_OUT_SELECT = (auto_conv_enable == 1) ? ana_auto_select : ana_reg_select; assign RD_ANA_CH = (auto_conv_enable == 1) ? ana_auto_rd_ch : ana_rd_command; assign RD_DYNODE_CH = (auto_conv_enable == 1) ? ana_auto_rd_dynode : dynode_rd_command; AllChannels AllDigitalChannels(.TO_CHIP_OR(channel_or), .TO_XY_GENERATOR(channel_xy), .FAST_DATA(data_fast), .SLOW_DATA(data_slow), .TEST_PULSE(TEST_PULSE | test_command), .ANODE_HIT(ANODE), .INTEGRATOR_FLAG(INTEGRATOR_FLAG), .PIX_ENABLE(pix_enable), .OR_ENABLE(or_enable), .XY_ENABLE(xy_enable), .DIGITAL_THRESHOLD(digital_threshold), .GTU_CLOCK(GTU_CLOCK), .GTU_SUM(gtu_sum), .RUN_ENABLE(run_enable), .ADDR_RD_FAST(addr_fast_read), .RD_FAST(rd_fast), .EN_FAST(en_fast), .ADDR_WR_FAST(addr_fast_write), .WR_TEST_FAST(wr_fast), .ADDR_RD_SLOW(addr_slow_read), .RD_SLOW(rd_slow), .EN_SLOW(en_slow), .ADDR_WR_SLOW(addr_slow_write), .WR_TEST_SLOW(wr_slow), .ID_FAST_1ST(id_fast_1st), .ID_FAST_MAIN(id_fast_main), .ID_SLOW_1ST(id_slow_1st), .ID_SLOW_MAIN(id_slow_main), .MEM_DATA_IN(wr_test_data), .TEST_MODE(test_mode), .CLOCK(CLOCK), .GLOBAL_RESET(reset | sync)); selector discr_selector(.DATA_OUT(DISCR_OUT), .DATA_IN(ANODE), .SELECT({3'b0, discr_out_select[4:0]}), .ENABLE(discr_out_select[5])); register_bank registers(.OUT0(), .OUT1(), .OUT2(), .OUT3(), .OUT4(), .OUT5(), .OUT6(), .OUT7(), .OUT8(), .OUT9(), .OUT10(), .OUT11(), .OUT12(), .OUT13(), .OUT14(), .OUT15(), .OUT16(), .OUT17(), .OUT18(), .OUT19(), .OUT20(), .OUT21(), .OUT22(), .OUT23(), .OUT24(), .OUT25(), .OUT26(), .OUT27(), .OUT28(), .OUT29(), .OUT30(), .OUT31(), .SDATA_OUT(dout_reg), .SDATA_IN(din_reg), .LD_SR(load_sr), .LD_REG(load_reg), .CLOCK(CLOCK), .RESET(reset)); ctrl_and_serial serial_interface( // I/O connections .DIN(DATA_IN), .DOUT(DATA_OUT), .D_C(D_C), .CK(CLOCK), .GA(GA), .RSTb(RSTb), // Registers connections .DOUT_REGS(din_reg), .DIN_REGS(dout_reg), .LD_REGS(load_reg), .LD_SHREG(load_sr), // Channels RAMs connections (digital counts) .ADDR_FAST_RD(addr_fast_read), .ADDR_FAST_WR(addr_fast_write), .ADDR_SLOW_RD(addr_slow_read), .ADDR_SLOW_WR(addr_slow_write), .RD_FAST(rd_fast), .EN_FAST(en_fast), .WR_FAST(wr_fast), .RD_SLOW(rd_slow), .EN_SLOW(en_slow), .WR_SLOW(wr_slow), .ID_FAST_1ST(id_fast_1st), .ID_FAST_MAIN(id_fast_main), .ID_SLOW_1ST(id_slow_1st), .ID_SLOW_MAIN(id_slow_main), .DATA_WR(wr_test_data), .DATA_FAST_RD({7'b0,data_fast}), .DATA_SLOW_RD(data_slow), // ADC interface RAMs connections (analog data) .DATA_ANA_RD(data_ana), .ADDR_ANA_RD(addr_ana_rd), .ADDR_ANA_WR(addr_ana_wr), .RD_ANA(rd_ana), .WR_ANA(wr_ana), .EN_ANA(en_ana), // Software commands (pulses) .TEST_CMD(test_command), .ANA_RD_CMD(ana_rd_command), .DYNODE_RD_CMD(dynode_rd_command), // Common signals .TEST_MODE(test_mode), .ADDRESSED(ADDRESSED), .RUN(RUN), .RUN_ENABLE(run_enable), .GTU_CLOCK(GTU_CLOCK), .GTU_SUM(gtu_sum), .SYNC(sync)); adc_if adc_interface(.ADDR_RD(addr_ana_rd), .ADDR_WR(addr_ana_wr), .RD(rd_ana), .WR(wr_ana), .EN(en_ana), .TEST(test_mode), .DIN(wr_test_data), .DOUT(data_ana), .RD_ANA_CH(ana_auto_rd_ch), .RD_DYNODE_CH(ana_auto_rd_dynode), .ANA_SELECT(ana_auto_select), .AUTO_CONV(auto_conv_enable), .ADC_CK_DIV2(adc_ck_div2), // from registers .N_CH(8'h`N_CH), .N_DYNODE(8'h1), .ADC_SDATA(ADC_SDATA), .ADC_CK(ADC_CK), .ADC_CSb(ADC_CSb), .RUN(run_enable), .CLOCK(CLOCK), .RESET(reset)); gtu_sum_generator gtu_sum_gen(.GTU_SUM(gtu_sum), .GTU_CLOCK(GTU_CLOCK), .GTU_SUM_PERIOD(gtu_sum_period), .CLOCK(CLOCK), .RESET(reset | sync)); xy_generator xy(.X(CHIP_X), .Y(CHIP_Y), .CH_XY(channel_xy)); or_generator fast_or(.CHIP_OR_OUT(CHIP_OR_OUT), .CHIP_OR_IN(CHIP_OR_IN), .CHANNEL_OR(channel_or)); endmodule