Memory Bus Interface Width: Every DDR
Memory bandwidth is the rate at which information might be learn from or saved into a semiconductor memory by a processor. Memory bandwidth is normally expressed in items of bytes/second, although this may differ for techniques with natural data sizes that aren't a multiple of the generally used 8-bit bytes. Memory bandwidth that is marketed for a given enhance memory retention or system is usually the utmost theoretical bandwidth. In observe the observed Memory Wave bandwidth might be less than (and is assured to not exceed) the advertised bandwidth. A variety of computer benchmarks exist to measure sustained memory bandwidth using a variety of entry patterns. These are meant to offer perception into the memory bandwidth that a system ought to sustain on varied classes of real purposes. 1. The bcopy convention: counts the quantity of information copied from one location in memory to another location per unit time. For example, copying 1 million bytes from one location in memory to another location in memory in one second would be counted as 1 million bytes per second.
The bcopy convention is self-constant, however shouldn't be simply prolonged to cowl cases with extra complex entry patterns, for example three reads and one write. 2. The Stream convention: sums the amount of information that the appliance code explicitly reads plus the amount of information that the application code explicitly writes. Using the previous 1 million byte copy example, the STREAM bandwidth would be counted as 1 million bytes read plus 1 million bytes written in a single second, for a complete of 2 million bytes per second. The STREAM convention is most straight tied to the consumer code, however might not depend all the info visitors that the hardware is actually required to perform. 3. The hardware convention: counts the precise quantity of knowledge learn or written by the hardware, whether or not the data movement was explicitly requested by the consumer code or not. Using the same 1 million byte copy instance, the hardware bandwidth on pc techniques with a write allocate cache coverage would include an extra 1 million bytes of visitors as a result of the hardware reads the goal array from Memory Wave into cache before performing the stores.
This gives a total of three million bytes per second truly transferred by the hardware. The hardware convention is most directly tied to the hardware, however might not represent the minimal amount of information traffic required to implement the consumer's code. Quantity of data transfers per clock: Two, within the case of "double knowledge price" (DDR, DDR2, DDR3, DDR4) memory. Memory bus (interface) width: Each DDR, DDR2, or DDR3 memory interface is 64 bits broad. Number of interfaces: Modern private computer systems sometimes use two memory interfaces (twin-channel mode) for an effective 128-bit bus width. This theoretical most memory bandwidth is referred to as the "burst price," which might not be sustainable. The naming convention for DDR, DDR2 and DDR3 modules specifies both a maximum velocity (e.g., DDR2-800) or a maximum bandwidth (e.g., PC2-6400). The velocity ranking (800) is not the maximum clock speed, but twice that (because of the doubled data rate).
The specified bandwidth (6400) is the utmost megabytes transferred per second utilizing a 64-bit width. In a twin-channel mode configuration, that is effectively a 128-bit width. Thus, the memory configuration in the instance may be simplified as: two DDR2-800 modules running in dual-channel mode. Two memory interfaces per module is a typical configuration for Pc system memory, however single-channel configurations are common in older, low-finish, or low-power devices. Some private computers and most fashionable graphics cards use more than two memory interfaces (e.g., four for Intel's LGA 2011 platform and the NVIDIA GeForce GTX 980). Excessive-performance graphics playing cards running many interfaces in parallel can attain very high whole memory bus width (e.g., 384 bits in the NVIDIA GeForce GTX TITAN and 512 bits within the AMD Radeon R9 290X using six and eight 64-bit interfaces respectively). In techniques with error-correcting memory (ECC), the extra width of the interfaces (typically seventy two somewhat than sixty four bits) will not be counted in bandwidth specs because the additional bits are unavailable to store person information. ECC bits are higher regarded as part of the memory hardware fairly than as information saved in that hardware.