Application Case 1—Hardware-Timed Simultaneously Updated I/O

Requirement

"My I/O must be hardware-timed. All output values need to simultaneously update at the arrival of the sample clock edge."

Solution

Use the Wait For Next Sample Clock VI (WFNSC) to verify that a new sample clock edge has not yet occurred.

Advantages

Restrictions

Read, process, and write operations are confined to the time available between the moment the device starts acquiring data and the moment the next sample clock edge arrives.

Sample Application

An example of this kind of application is an analog control loop that reads samples from a specific number of analog input channels, processes the data using a control algorithm (such as PID), and writes new control values to the analog output channels.

Sample Implementation

Sample Block Diagram

Notes