Application Case 2—Hardware-Timed Simultaneously Updated I/O with Data Exchanges between Time-Critical and Non-Time-Critical Loops

Requirement

"My I/O needs to be hardware-timed. All output values need to simultaneously update at the arrival of the sample clock edge. I need to exchange data between my time-critical loop and my lower-priority processes."

Solution

Advantages

Restrictions

Read, process, and write operations are confined to the amount of time available between the moment the device starts acquiring data and the moment the next sample clock edge arrives.

Sample Application

An example of this kind of application is an analog control loop that reads samples from a specific number of analog input channels, processes the data using a control algorithm (such as PID), and writes the new control values to the analog output channels. The application uses a real-time FIFO to stop the control loop based on a Boolean value provided by a lower-priority process. A similar approach can employ the use of real-time FIFOs to vary the PID parameters on the fly, or to transfer acquired and control output values to lower-priority processes for data logging and remote monitoring.

Sample Timing Diagram

Sample Implementation

Sample Block Diagram

Notes