A few information about the structure of the circuit inside the FPGA in the glueboard. The FPGA contains the following blocks: 1) prescaler the prescaler divides the local clock by 5 to produce the xclk signal (pin 58), it always runs, provided the reset is not active (this is a simple check that the fpga has been properly programmed) 2) register to enable I2C and JTAG hubs: ADDRESS 10H (decimal 16) the register contains 6 bits with the following functions: bit 0: I2C channel 0 enable (0 means disabled) bit 1 " " 1 " bit 2 " " 2 " bit 3 " " 3 " bit 4 bus switch enable (0 means disabled) this bit is internally inverted to cope with the inverted enable of the chip bit 5 JTAG HUB scansta111 enable (0 means disabled) these bit must be set to 1 before being able to use local, I2C and JTAG buses 3) I2C controller: (PCF8584 by Philips) The address decoding for the I2C controller located in the glueboard is made inside the FPGA. it responds to base address 08H (decimal 8) This controller is connected to the I2C hub type PCA9516 4) JTAG controller: (74LVT8980) The address decoding for the JTAG controller located in the glueboard is made inside the FPGA. it responds to base address 20H (decimal 32) This controller is connected to the Jyag hub type SCANSTA111 All these devices are mapped on address space 0 of the PLX 9030 and pin CS0 is used in decoding the address. These are very preliminary specifications and as such are subject to change, anyway it is hoped modifications will be very small. Flavio Fontanelli