TDC test set-up

The test bench described in this note has been used to verify the ITB board before the installation in BaBar, and to debug broken boards.
With this test is possible to verify:

The set-up, showed in the fig., consists of:

The fan-OUT board has been designed to pulse all 96 channels together. Each channel can be selected by  switches and 3 different input channels can be used.

The LSA generates the input command according the BaBar protocol, and reads back the output data.
An external pulse generator is used to synchronize the LSA and to generate the input command to the ITB board.
A second pulse generator is used to produce input data at different rates, and to produce an external trigger to the LSA.
The input data frequency has been varied up to 300KHz, which is the maximum rate supported by the TDC chip with 12 ms latency.

To check the good performance of the board, the right format of the
output data is read on the LSA screen.

To connect the LSA 3 different pods are used:

10460A TTL clock pod to input the 59.5MHz clock and the trigger.
10462A TTL/CMOS data pod to send the command to the ITB.
16517-63202 master pod to receive the data from the ITB.
For the  cable length, check the above fig.